FPGA 学习 08 BCD码

BCD_Counter.v文件

module BCD_Counter( Clk , Cin , Rst_n , Cout , q ); input Clk ; input Cin ; input Rst_n ; output Cout ; output [3:0]q ; reg [3:0]cnt ; //always block always@(posedge Clk or negedge Rst_n) if(Rst_n== 1'b0) cnt <= 0 ; else if(Cin == 1'b1) begin if(cnt == 4'd9) cnt <= 0 ; else cnt <= cnt + 1'b1 ; end else cnt <= cnt ; /* //always block always@(posedge Clk or negedge Rst_n) if(Rst_n== 1'b0) Cout <= 0 ; else if(cnt == 4'd8 && Cin == 1'b1) Cout <= 1'b1 ; else Cout <= 1'b0 ; */ //assign Cout = (cnt == 4'd9 && Cin == 1'b1); assign Cout = (cnt == 4'd9); assign q = cnt ; endmodule

BCD_Counter_tb.v 文件

`timescale 1ns/1ns `define clock_period 20 module BCD_Counter_tb; reg Clk ; reg Cin ; reg Rst_n ; wire Cout ; wire [3:0]q ; BCD_Counter BCD_Counter0( .Clk(Clk) , .Cin(Cin) , .Rst_n(Rst_n) , .Cout(Cout) , .q(q) ); initial Clk = 0 ; always #(`clock_period/2) Clk = ~Clk ; initial begin Rst_n = 1'b0 ; Cin = 1'b0 ; #(`clock_period *20); Rst_n = 1'b1 ; repeat(30) begin #(`clock_period * 5); Cin = 1'b1 ; #(`clock_period * 1); Cin = 1'b0 ; end #(`clock_period * 200); $stop ; end endmodule

BCD_Counter_top.v 文件

module BCD_Counter_top( Clk , Cin , Rst_n , Cout , q ); input Clk ; input Cin ; input Rst_n ; output Cout ; output [11:0]q ; wire cout0 ; wire cout1 ; //wire {3:0}q0,q1,q2; //assign q ={q2,q1,q0} ; //位拼接操作 BCD_Counter BCD_Counter0( .Clk(Clk) , .Cin(Cin) , .Rst_n(Rst_n) , .Cout(cout0) , .q(q[3:0]) ); BCD_Counter BCD_Counter1( .Clk(Clk) , .Cin(cout0) , .Rst_n(Rst_n) , .Cout(cout1) , .q(q[7:4]) ); BCD_Counter BCD_Counter2( .Clk(Clk) , .Cin(cout1) , .Rst_n(Rst_n) , .Cout(Cout) , .q(q[11:8]) ); endmodule

BCD_Counter_top_tb.v 文件

`timescale 1ns/1ns `define clock_period 20 module BCD_Counter_top_tb; reg Clk ; reg Cin ; reg Rst_n ; wire Cout ; wire [11:0]q ; BCD_Counter_top BCD_Counter_top_0( .Clk(Clk) , .Cin(Cin) , .Rst_n(Rst_n) , .Cout(Cout) , .q(q) ); initial Clk = 0 ; always #(`clock_period/2) Clk = ~Clk ; initial begin Rst_n = 1'b0 ; Cin = 1'b0 ; #(`clock_period *20); Rst_n = 1'b1 ; /* repeat(4300) begin #(`clock_period * 1); Cin = 1'b1 ; #(`clock_period * 1); Cin = 1'b0 ; end */ #(`clock_period * 200); Cin = 1'b1 ; #(`clock_period * 3200); $stop ; end endmodule