1.程序 module fsm(clk,clr,a,y); input clk,clr,a; output y; reg y; reg[2:0]current_state,next_state; parameter s0=3’b000,s1=3’b001,s2=3’b010,s3=3’b011,s4=3’b100; always@(posedge clk or negedge clr) begin if(clk) current_state<=s0; else current_state<=next_state; end always@(current_state or a) begin case(current_state) s0:next_state=(a1)?s1:s0; s1:next_state=(a0)?s2:s0; s2:next_state=(a1)?s3:s0; s3:next_state=(a1)?s4:s0; s4:next_state=(a==0)?s2:s0; default:next_state=s0; endcase end always@(current_state) begin case(current_state) s4:y=1; default:y=0; endcase end endmodule
乱码部分:
2.testbench `timescale 1 ns/ 1 ps module fsm_tb; reg a; reg clk; reg clr; // wires wire y;
// assign statements (if any) fsm i1 ( // port map - connection between master ports and signals/registers .a(a), .clk(clk), .clr(clr), .y(y) ); initial begin a=0; clk=0; clr=1; #5 clr=0; #5 clr=1; #10 a=1; #10 a=0; #10 a=1; #10 a=1; #10 a=1; #10 a=1; #10 a=0; #10 a=1; #10 a=1; #10 a=1; #10 a=0; #10 a=1; #10 a=1; #10 a=1; end always #5 clk=~clk;
endmodule
3.仿真图
