H27Q1T8YEB9R-BCF学习笔记

本文包含SK Hynix Flash芯片 H27Q1T8YEB9R-BCF 相关资料和datasheet学习笔记。本文也只讲述宏观的功能。算是Flash芯片的入门。有不对的地方请指正。 Email: zhengxjie1@163.com

目录

1. summary description1.1 part number information1.2 定义说明1.3 block diagram 2.Physical Interface and Measurement condition2.1 package information(没太懂)2.2Toggle DDR Timing Parameters Description 3.Memory Organization3.1 Memory Size3.2 Target Memory Organization3.3 Addressing 4.Function Description4.1 Power Transition Sequence4.2 Interface/Timing Mode Transitions4.3 Mode Selection4.4 基本时序4.4.1 command latch cycle4.4.2 address latch cycle4.4.3 basic data input timing4.4.4 basic data output timing4.4.6 获取芯片ID4.4.7 read status(稀里糊涂) 4.4.8 Set feature4.4.9 Get feature4.4.10 Page Program Operation 5.Memory Operations

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1. summary description

1.1 part number information

本部分仅仅说明该芯片的信息。完整对应表见上传资源(待审核)

H27Q1T8YEB9RMemoryPower supplyDensityInput/Output Bus widthDie stackConfigurationGenerationPackagePackage materialSKHynix NAND Flash3.3V Vcc 1.8V VccQ [1]1Tbitx8 input/outputc-MLC ODP[2]4CE & 4R/B,dual channel3rd152-fBGAGreen(lead & Halogen free[3]) BCFBad blockTemperatureInput/output speedInclude bad blockCommercial temp. product200Hz(400Mb/s)

注： [1] VCC为Flash Controller的供电电压，VCCQ为Memory和Controller之间I/O的供电。 [2] 本文介绍的为152Ball fBGA ODP封装 [3] 无卤素添加

1.2 定义说明

Address:包含 column addr(2 cycles)和row addr(3 cycles)。行地址定义了地址的page，block，LUN。列地址定义了page中具体的byte。列地址的最小位(Least Significant Bit)总是0。 Page:The smallest addressable unit for the Read and the Program operations. Block:包含多个page，同时是Erase操作的最小单元。 Page register：transfer data to and from the Flash Array Defect area：工厂标记出厂缺陷的区域。(refer to the “Factory Defect Mapping”) Device:The packaged NAND unit. 可以包含多个Target Target:拥有自己CE 信号的独立NAND Flash组成部分。 LUN：Logical Unit Number；能独立执行命令和报告状态的最小单位。一个CE信号管理一个或者多个LUN。 SR[x](Read Status):SR是一个LUN的状态寄存器。(具体每位的含义refer to “Read Status Operation”)

1.3 block diagram

NAND Flash Die Functional Block Diagram

pin description

Pin NameDescription$\text{DQ[7:0]}$DATA INPUTS/OUTPUTS 用于输入command/addr/data以及在读操作中输出data。当芯片未被选中或者输出被disable，管脚变为高阻态(high-z)$\text{CLE}$COMMAND LATCH ENABLE 当为高电平时候，command在 $\overline{\text{WE}}$ 信号的上升沿被锁存到command register$\text{ALE}$ADDRESS LATCH ENABLE 当为高电平时候，addr在 $\overline{\text{WE}}$ 信号的上升沿被锁存到内部的address register$\overline{\text{CE}}$CHIP ENABLE 这是device selection control。当设备处于busy， $\overline{\text{CE}}$高并不会返回待机模式(standby mode)$\overline{\text{RE}}$Read Enable (True). RE_t 为serial data-out control 。Data is valid after tDQSRE of rising edge & falling edge of $\overline{\text{RE}}$。使用RE_c来提供差分对信号。$\text{RE}$Read Enable Complement. RE_c $\overline{\text{RE}}$的补充信号$\overline{\text{WE}}$WRITE ENABLE The $\overline{\text{WE}}$ input controls writes to the DQ port. Commands, addresses are latched on the rising edge of the $\overline{\text{WE}}$ pulse.$\overline{\text{WP}}$WRITE PROTECT active low的时候就进入写保护，只能进行read$\text{R}$/$\overline{\text{B}}$READY/BUSY OUTPUT 表明设备操作状态。低的时候，表明program/erase/random read操作正在进行中，完成后会返回到高状态。$\text{DQS}$DATA STROBE. DQS_t 输出和DQS的上下沿对齐$\overline{\text{DQS}}$Data Strobe Complement. DQS_c $\text{DQS}$ 的补充信号$\text{Vcc}$POWER power supply for device$\text{VccQ}$DQ POWER power supply for input and/or output signals$\text{Vss}$GROUND $\text{VssQ}$DQ GROUND power supply ground$\text{VREF}$Voltage Reference This signal is used as an external voltage reference for input and DQ signals when VccQ 1.8V is selected. VREF must be used when data inputs/outputs is the speed of 400Mbps and over.$\text{Vpp}$EXTERNAL HIGH VOLTAGE $\text{NC}$NO CONNECTION Lead is not internally connected.$\text{NU}$NOT USE Nothing should be connected with it.

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2.Physical Interface and Measurement condition

2.1 package information(没太懂)

2.2Toggle DDR Timing Parameters Description

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3.Memory Organization

3.1 Memory Size

实际上block不仅仅有4096个，还有额外的88个block确保有足够的block数目。

注意：

16GByte: single die stack32GByte: two-die stack that operates as two independant 128Gbit devices64GByte: four-die stack that operates as four independant 128Gbit devices128GByte: eight-die stack that operates as four independant 128Gbit devices（不是应该256Gbit吗？datasheet中写的128Gbit）

3.2 Target Memory Organization

A target is controlled by one CE signal. A target is organized into one or more logical units (LUNs).提高并行度。

3.3 Addressing

3.3.1 single die addressing

这里为容量为128Gbit的die，program操作需要5个byte的地址进行确定。下面是5个周期对应的各位以及各位的含义。注意： [1] L表示必须为0 [2] 该设备(device)忽略所有必须之外的额外地址输入。

3.3.2 Plane Address

为了multi-plane设备。在block的低位用于表示plane address。

3.3.3 Block Defect 标注

如果标注位不是0FF的话，就说明是defective。注意的是，标志位位如图的4个byte。

3.3.4 Addressing For Program Operation

paired page是MLC引入的。将一个物理cell的状态分配到两个page之中。具体参考链接.需要注意的是如果program失败(比如power-down)，不仅仅是在program的page数据损坏，也会导致paired pages上的数据损坏。

注意本图仅仅为部分表，一个block有256个page。

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4.Function Description

4.1 Power Transition Sequence

4.1.1 Power Up Sequence 4.1.2 Power Down Sequence(稀里糊涂)

下图表示up-operations-down的前后初始化时序图。

4.2 Interface/Timing Mode Transitions

4.2.1 SDR Transition from DDR

使用EF转换，FF用于reset

4.2.2 MLC to SLC transition

4.3 Mode Selection

4.4 基本时序

4.4.1 command latch cycle

4.4.2 address latch cycle

4.4.3 basic data input timing

4.4.4 basic data output timing

4.4.6 获取芯片ID

4.4.7 read status(稀里糊涂)

这二者啥区别？？？是否initial为啥造成这些区别？

(1) read status cycle

(2) Read Status cycle before Toggle DDR setting at Initialization sequence by FFh command

4.4.8 Set feature

4.4.9 Get feature

4.4.10 Page Program Operation

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5.Memory Operations

set feature具体2nd cycle输入以及含义 - 62页 read ID operations具体对应 - 67页 read status definition - 68页

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详细资料：H27Q1T8YEB9R-BCF 注：密码：qeg7