EDA某次作业的记录
利用书上已给出的一位全加器代码,调用八次一位全加器构成一个八位全加器。
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY e_adder IS PORT ( a,b: IN STD_LOGIC_VECTOR(7 DOWNTO 0); c : IN STD_LOGIC; s: OUT STD_LOGIC_VECTOR(8 DOWNTO 0); ); END ENTITY e_adder; ARCHITECTURE ed1 OF e_adder IS COMPONENT f_adder PORT (ain,bin,cin:IN STD_LOGIC; cout,sum:OUT STD_LOGIC); END COMPONENT ; SIGNAL net1,net2,net3,net4,net5,net6,net7:STD_LOGIC; BEGIN u1: f_adder PORT MAP ( ain =>a(0),bin=>b(0),cin=>c,sum=>s(0),cout=>net1;); u2: f_adder PORT MAP ( ain =>a(1),bin=>b(1),cin=>net1,sum=>s(1),cout=>net2;); u3: f_adder PORT MAP ( ain =>a(2),bin=>b(2),cin=>net2,sum=>s(2),cout=>net3;); u4: f_adder PORT MAP ( ain =>a(3),bin=>b(3),cin=>net3,sum=>s(3),cout=>net4;); u5: f_adder PORT MAP ( ain =>a(4),bin=>b(4),cin=>net4,sum=>s(4),cout=>net5;); u6: f_adder PORT MAP ( ain =>a(5),bin=>b(5),cin=>net5,sum=>s(5),cout=>net6;); u7: f_adder PORT MAP ( ain =>a(6),bin=>b(6),cin=>net6,sum=>s(6),cout=>net7;); u8: f_adder PORT MAP ( ain =>a(7),bin=>b(7),cin=>net7,sum=>s(7),cout=>s(8);); END ARCHITECTURE ed1;
